I. Field of the Disclosure
The technology of the disclosure relates generally to standard cell circuits, and particularly to reducing area of standard cell circuits.
II. Background
Processor-based computer systems can include a vast array of integrated circuits (ICs). Each IC has a complex layout design comprised of multiple IC devices. Standard cell circuits are often employed to assist in making the design of ICs less complex and more manageable. In particular, standard cell circuits provide a designer with pre-designed cells corresponding to commonly used IC devices that conform to specific design rules of a chosen technology. As non-limiting examples, standard cell circuits may include gates, inverters, multiplexers, and adders. Using standard cell circuits enables a designer to create ICs having consistent layout designs, thereby creating a more uniform and less complex layout design across multiple ICs, as compared to custom designing each circuit.
Conventional standard cell circuits are fabricated using process technologies that form device elements with a pre-defined technology node size. For example, a process technology may be employed to fabricate a conventional standard cell circuit with device elements approximately fourteen (14) nanometers or ten (10) nm wide. Process technologies continue to enable decreased technology node size, which allows a higher number of device elements, such as transistors, to be disposed in less area within a circuit. As technology node size scales down, metal lines within a conventional standard cell circuit also scale down to reduce the overall area of a conventional standard cell circuit. For example, as the technology node size is reduced, metal lines disposed in both an x-coordinate and y-coordinate direction may be scaled down by approximately thirty percent (30%) such that the conventional standard cell circuit has a scaling factor of approximately 0.7 in each direction. The total scaling factor of the conventional standard cell circuit is approximately equal to fifty percent (50%) (i.e., 0.7 in the x-coordinate direction×0.7 in the y-coordinate direction=49%, approximately 50%). Therefore, a conventional standard cell circuit can achieve an area reduction of approximately 50% in response to a scaled down technology node size.
However, as the technology node size scales down to ten (10) nm and below, metal lines within a conventional standard cell circuit cannot continue to scale by 30% percent due to gate pitch and metal pitch limitations. Thus, conventional standard cell circuits cannot achieve a desired area reduction of approximately 50% at technology node sizes of 10 nm or less.